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ltc6087/LTC6088 1 60878fa features applications description dual/quad 14mhz, rail-to-rail cmos ampli ers the ltc ? 6087/LTC6088 are dual/quad, low noise, low offset, rail-to-rail input/output, unity-gain stable cmos operational ampli? ers that feature 1pa of input bias cur- rent. a 14mhz gain bandwidth and 7.2v/s slew rate, combined with low noise (10nv/ hz ) and a low 0.75mv offset, make the ltc6087/LTC6088 useful in a variety of applications. the 1.1ma supply current and the shutdown mode are ideal for signal processing applications which demand performance with minimal power. the ltc6087/LTC6088 has an output stage which swings within 30mv of either supply rail to maximize signal dy- namic range in low supply applications. the input common mode range includes the entire supply voltage. these op amps are speci? ed on power supply voltages of 3v and 5v from C40c to 125c. the dual ampli? er ltc6087 is available in 8-lead msop and 10-lead dfn packages. the quad ampli? er LTC6088 is available in 16-lead ssop and dfn packages. single supply shock/vibration sensor ampli? er n low offset voltage: 750v maximum n low offset drift: 5v/c maximum n input bias current: 1pa (typical at 25c) 15pa (typical at 85c) n rail-to-rail inputs and outputs n gain bandwidth product: 14mhz n cmrr: 70db minimum n psrr: 93db minimum n input noise voltage density: 12nv/ hz n supply current: 1.1ma per amp n shutdown current: 2.3a per amp n 2.7v to 5.5v operation voltage n available in 8-lead msop and 10-lead dfn packages (ltc6087), 16-lead ssop and dfn packages (LTC6088) n portable test equipment n medical equipment n audio n data acquisition n high impedance transducer ampli? er ltc6087 input bias current vs temperature l , lt, ltc and ltm are registered trademarks of linear technology corporation. all other trademarks are the property of their respective owners. typical application C + 1/2 ltc6087 murata shock sensor pkgs-00mx1 520pf, 0.57pc/g www.murata.com C + 1/2 ltc6087 v s 1k 1% 100k 1% 60878 ta01a v out 570mv/g 16hz to 10khz v s = 2.7v to 5.5v v s 0.1 f 100k 100k 100m 100pf temperature ( c) 25 40 input bias current (pa) 10 100 1000 v s = 5v v cm = 2.5v 55 70 85 100 115 130 60878 ta01b 1
ltc6087/LTC6088 2 60878fa absolute maximum ratings total supply voltage (v + to v C ) ...................................6v input voltage ...................................................... v C to v + output short-circuit duration (note 2) ............ inde? nite operating temperature range (note 3) ltc6087c/LTC6088c ........................... C40c to 85c ltc6087h/LTC6088h ......................... C40c to 125c (note 1) 1 2 3 4 outa Cina +ina v C 8 7 6 5 v+ outb Cinb +inb top view ms8 package 8-lead plastic msop + C a + C b t jmax = 150c, ja = 200c/w top view 11 dd package 10-lead ( 3mm 3mm ) plastic dfn 10 9 6 7 8 4 5 3 2 1 v+ outb Cinb +inb shdnb outa Cina +ina vC shdna + C a + C b t jmax = 150c, ja = 43c/w exposed pad (pin 11) is v C , must be soldered to pcb gn package 16-lead plastic ssop narrow 1 2 3 4 5 6 7 8 top view 16 15 14 13 12 11 10 9 outa Cina +ina v + +inb Cinb outb nc outd Cind +ind v C +inc Cinc outc nc + C + C + C + C a bc d t jmax = 150c, ja = 110c/w 16 15 14 13 12 11 10 9 17 1 2 3 4 5 6 7 8 outd Cind +ind v C +inc Cinc outc nc outa Cina +ina v + +inb Cinb outb nc top view dhc package 16-lead ( 5mm 3mm ) plastic dfn + C + C + C + C a bc d t jmax = 150c, ja = 43c/w exposed pad (pin 17) is v C , must be soldered to pcb speci? ed temperature range (note 4) ltc6087c/LTC6088c ............................... 0c to 70c ltc6087h/LTC6088h ......................... C40c to 125c junction temperature ........................................... 150c storage temperature range ................... C65c to 150c lead temperature (soldering, 10 sec) ms8, gn16 only ............................................... 300c pin configuration
ltc6087/LTC6088 3 60878fa order information the l denotes the speci? cations which apply over the full speci? ed temperature range, otherwise speci? cations are at t a = 25c. test conditions are v + = 3v, v ? = 0v, v cm = 0.5v unless otherwise noted. symbol parameter conditions c suffix h suffix units min typ max min typ max v os offset voltage (note 5) ltc6087ms8, LTC6088gn ltc6087dd, LTC6088dhc ltc6087ms8, LTC6088gn ltc6087dd, LTC6088dhc l l 330 330 750 1100 900 1350 330 330 750 1100 1100 1600 v v v v 6v os /6 t input offset voltage drift (note 6) ltc6087ms8, LTC6088gn ltc6087dd, LTC6088dhc l l 2 2 5 5 2 2 5 5 v/c v/c i b input bias current (notes 5, 7) guaranteed by 5v test
ltc6087/LTC6088 4 60878fa electrical characteristics the l denotes the speci? cations which apply over the full speci? ed temperature range, otherwise speci? cations are at t a = 25c. test conditions are v + = 3v, v C = 0v, v cm = 0.5v unless otherwise noted. symbol parameter conditions c suffix h suffix units min typ max min typ max a vol large-signal voltage gain r load = 10k, 0.5v v out 2.5v o 500 300 3000 500 30 3000 v/mv v/mv i sc output short-circuit current source and sink o 25 21 35 25 18 35 ma ma sr slew rate a v = 1 7.2 7.2 v/s gbw gain bandwidth product (f test = 20khz) r load = 50k o 10 9 14 10 8 14 mhz mhz 0 phase margin r l = 10k, c l = 45pf, a v = 1 45 45 deg t s settling time 0.1% v step = 2v, a v = C1, r l = 1k 1 1 s i s supply current (per ampli? er) no load o 0.85 0.80 1.05 1.05 1.20 1.25 0.85 0.75 1.05 1.05 1.20 1.35 ma ma shutdown current (per ampli? er) shutdown, v shdn 0.8v o 0.2 1 0.2 1 a v s supply voltage range guaranteed by the psrr test o 2.7 5.5 2.7 5.5 v channel separation f s = 10khz C120 C120 db shutdown logic shdn high shdn low o o 2 0.8 2 0.8 v v t on turn-on time v shdn = 0.8v to 2v 6 6 s t off turn-off time v shdn = 2v to 0.8v 2 2 s leakage of shdn pin v shdn = 0v o 0.1 0.5 0.1 0.5 a the l denotes the speci? cations which apply over the full speci? ed temperature range, otherwise speci? cations are at t a = 25c. test conditions are v + = 5v, v C = 0v, v cm = 0.5v unless otherwise noted. symbol parameter conditions c suffix h suffix units min typ max min typ max v os offset voltage (note 5) ltc6087ms8, LTC6088gn ltc6087dd, LTC6088dhc ltc6087ms8, LTC6088gn ltc6087dd, LTC6088dhc l l 330 330 750 1100 900 1350 330 330 750 1100 1100 1600 v v v v v os / t input offset voltage drift (note 6) ltc6087ms8, LTC6088gn ltc6087dd, LTC6088dhc l l 2 2 5 5 2 2 5 5 v/c v/c i b input bias current (notes 5, 7) o 1 40 1 500 pa na i os input offset current (notes 5, 7) o 0.5 30 0.5 150 pa pa e n input noise voltage density f = 1khz f = 10khz 12 10 12 10 nv/ hz nv/ hz input noise voltage 0.1hz to 10hz 2.5 2.5 v p-p i n input noise current density (note 8) f = 1hz 0.56 0.56 fa/ hz input common mode range o v C v + v C v + v c in input capacitance differential mode common mode f = 100khz 2.7 4.2 2.7 4.2 pf pf
ltc6087/LTC6088 5 60878fa electrical characteristics the l denotes the speci? cations which apply over the full speci? ed temperature range, otherwise speci? cations are at t a = 25c. test conditions are v + = 5v, v C = 0v, v cm = 0.5v unless otherwise noted. symbol parameter conditions c suffix h suffix units min typ max min typ max cmrr common mode rejection ratio 0v v cm 5v o 70 68 84 70 66 84 db db psrr power supply rejection ratio v s = 2.7v to 5.5v o 93 90 115 93 85 115 db db v out output voltage, high (referred to v + ) no load i source = 1ma i source = 5ma o o o 5 20 110 15 50 190 5 20 110 20 50 210 mv mv mv output voltage, low (referred to v C ) no load i sink = 1ma i sink = 5ma o o o 5 20 110 25 50 200 5 20 110 30 60 220 mv mv mv a vol large-signal voltage gain r load = 10k, 0.5v v out 4.5v o 1000 500 6000 1000 50 6000 v/mv v/mv i sc output short-circuit current source and sink o 28 25 45 28 22 45 ma ma sr slew rate a v = 1 7.2 7.2 v/s gbw gain bandwidth product (f test = 20khz) r load = 50k o 10 9 14 10 8 14 mhz mhz 0 phase margin r l = 10k, c l = 45pf, a v = 1 47 47 deg t s settling time 0.1% v step = 2v, a v = C1, r l = 1k 0.8 0.8 s i s supply current (per ampli? er) no load o 0.85 0.80 1.05 1.05 1.25 1.30 0.85 0.75 1.05 1.05 1.25 1.40 ma ma shutdown current (per ampli? er) shutdown, v shdn 1.2v o 2.3 5 2.3 5 a v s supply voltage range guaranteed by the psrr test o 2.7 5.5 2.7 5.5 v channel separation f s = 10khz C120 C120 db shutdown logic shdn high shdn low o o 3.5 1.2 3.5 1.2 v v t on turn-on time v shdn = 1.2v to 3.5v 6 6 s t off turn-off time v shdn = 3.5v to 1.2v 2 2 s leakage of shdn pin v shdn = 0v o 0.4 1 0.4 1 a note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: a heat sink may be required to keep the junction temperature below the absolute maximum. this depends on the power supply voltage and the total output current. note 3: the ltc6087c/LTC6088c are guaranteed functional over the operating temperature range of C40c to 85c. the ltc6087h/LTC6088h are guaranteed functional over the operating temperature range of C40c to 125c. note 4: the ltc6087c/LTC6088c are guaranteed to meet speci? ed performance from 0c to 70c. the ltc6087c/LTC6088c are designed, characterized and expected to meet speci? ed performance from C40c to 125oc but are not tested or qa sampled at these temperatures. the ltc6087h/LTC6088h are guaranteed to meet speci? ed performance from C40c to 125c. note 5: esd (electrostatic discharge) sensitive device. esd protection devices are used extensively internal to the ltc6087/LTC6088; however, high electrostatic discharge can damage or degrade the device. use proper esd handling precautions. note 6: this parameter is not 100% tested. note 7: this speci? cation is limited by high speed automated test capability. see typical performance characteristic curves for actual performance. note 8: current noise is calculated from: i n = 2qi b , where q = 1.6 ? 10 C19 coulombs.
ltc6087/LTC6088 6 60878fa typical performance characteristics v os distribution v os vs v cm v os drift distribution input bias current vs common mode voltage input noise voltage vs frequency 0.1hz to 10hz output voltage noise output voltage swing vs load current supply current vs supply voltage input noise current vs frequency v os (mv) C1 0 percentage of units (%) 2 4 6 8 12 C0.7 C0.4 C0.1 0.2 0.5 60878 g01 0.8 10 ltc6087ms8 v s = 5v v cm = 0.5v t a = 25 c v cm (v) 0 v os (mv) 0.2 0.6 1.0 4 60878 g02 C0.2 C0.6 0 0.4 0.8 C0.4 C0.8 C1.0 1 0.5 2 1.5 3 3.5 4.5 2.5 5 v s = 5v t a = 25 c representative parts distribution ( v/ c) C2 percent of units (%) 14 16 18 20 22 1.2 60878 g03 8 10 12 2 4 6 0 C1.2 C0.4 0.4 2.0 2.8 ltc6087ms8 v s = 5v v cm = 2.5v t a = C40 c to 125 c common mode voltage (v) 0 0.5 input bias current (pa) 0.1 1 10 100 1.5 2.5 3.5 12344.55 60878 g05 0.01 1000 10000 v s = 5v t a = 125 c t a = 85 c t a = 25 c frequency (hz) 30 90 100 20 10 80 50 70 60 40 10 1k 10k 100k 60878 g06 0 100 input noise voltage (nv/ hz) v s = 5v v cm = 2.5v t a = 25 c time (1s/div) input noise voltage (1 v/div) 60878 g07 v s = 5v v cm = 2.5v frequency (hz) 100 noise current (fa/ hz) 200 300 400 500 1 100 1000 100000 60878 g04 0 10 10000 load current (ma) 0.1 2.0 output voltage swing (v) 2.5 3.0 3.5 4.0 1 10 100 60878 g08 1.5 1.0 0.5 0 4.5 5.0 v s = 5v v cm = 2.5v t a = 125 c t a = 25 c t a = C55 c source sink supply voltage (v) 0 supply current (ma) 0.4 0.8 1.2 0.2 0.6 1.0 1234 69878 g09 5.5 0.5 0 1.5 2.5 3.5 4.5 5 per amplifier v cm = 0.5v t a = 25 c
ltc6087/LTC6088 7 60878fa typical performance characteristics supply current vs temperature open-loop gain vs frequency cmrr vs frequency psrr vs frequency output impedance vs frequency small-signal response small-signal response large-signal response large-signal response temperature ( c) C25 supply current (ma) 1.1 1.3 1.5 95 60878 g10 0.9 0.7 1.0 1.2 1.4 0.8 0.6 0.5 5 35 65 C10 C40 110 20 50 80 125 per amplifier v cm = 0.5v v s = 5v v s = 3v frequency (hz) 10 gain (db) phase (deg) 70 80 0 C10 60 30 50 40 20 10k 1m 10m 100m 60878 g11 C20 C20 100 120 C40 C60 80 20 60 40 0 C80 100k v s = 5v v s = 3v c l = 5pf r l = 1k v cm = v s /2 t a = 25 c phase gain frequency (hz) 10 20 cmrr (db) 30 40 50 70 60 100 90 80 10k 1m 10m 100m 60878 g12 C10 0 100k 110 v s = 5v v cm = 2.5v r l = 1k t a = 25 c frequency (hz) 1k 40 psrr (db) 50 60 70 80 10k 100k 1m 10m 100m 60878 g13 30 20 10 0 C10 90 100 positive supply v s = 5v v cm = 2.5v t a = 25 c negative supply frequency (hz) 10k 100k 0.001 output impedance ( ) 1 1000 1m 10m 100m 60878 g14 0.1 0.01 10 100 v s = 5v v cm = 2.5v t a = 25 c a v = 10 a v = 1 a v = 2 200ns/div v s = 5v a v = 1 r l = 60878 g15 100mv/div 200ns/div v s = 5v a v = 1 r l = c l = 33pf 100mv/div 60878 g16 2 s/div v s = 5v a v = 1 r l = 1v/div 60878 g17 1 s/div v s = 5v a v = C1 r l = 1k 1v/div 60878 g18
ltc6087/LTC6088 8 60878fa typical performance characteristics overshoot vs capacitive load channel separation vs frequency total harmonic distortion + noise vs load resistance total harmonic distortion + noise vs frequency total harmonic distortion + noise vs output voltage disabled output impedance vs frequency overshoot vs capacitive load total harmonic distortion + noise vs frequency frequency (hz) 10 output impedance (k ) 100 1000 100000 1000000 100 10k 100k 10m 60878 g20 1 1k 1m 10000 0.1 v s = 5v v cm = 1v a v = 1 t a = 25 c capacitive load (pf) 10 0 overshoot (%) 50 40 30 20 10 60 80 100 1000 60878 g21 70 v s = 5v v cm = 2.5v a v = 1 + C r s c l r s = 10 r s = 50 capacitive load (pf) 10 0 overshoot (%) 25 20 15 10 5 30 40 100 1000 60878 g22 35 v s = 5v v cm = 2.5v a v = C1 r s = 10 r s = 50 r s 1k 1k 30pf c l + C frequency (mhz) C120 channel separaton (db) C110 C105 C95 C90 0.01 1 10 100 60878 g23 C130 0.1 C100 C115 C125 v s = 5v v cm = 2.5v t a = 25 c frequency (khz) 0.01 thd + noise (%) 0.1 0.01 1 10 100 60878 g24 0.001 0.1 1 a v = 1, v in = 1v p-p a v = C2, v in = 1v p-p a v = 1, v in = 2v p-p a v = 2, v in = 1v p-p v s = 3v v cm = 1.5v r l = 10k frequency (khz) 0.01 0.001 thd + noise (%) 0.01 0.1 1 0.1 10 100 60878 g25 a v = 1, v in = 1v p-p a v = C2, v in = 1v p-p a v = 1, v in = 2v p-p a v = 2, v in = 1v p-p v s = 5v v cm = 2.5v r l = 10k output voltage (v p-p ) 0 0.5 1 2 2.5 3 4 4.5 0.0001 thd + noise (%) 0.01 0.1 1.5 3.5 5 60878 g26 0.001 v s = 3v at 20khz v s = 5v at 20khz v s = 5v at 1khz v s = 3v at 1khz r l = 10k v cm = v s /2 a v = 1 load resistance to ground (k ) 0.1 0.0001 thd + noise (%) 0.001 0.01 0.1 1 10 100 60878 g27 v s = 3v, v in = 1v p-p a v = 1 v cm = v s /2 at 1khz v s = 5v, v in = 2v p-p
ltc6087/LTC6088 9 60878fa pin functions out: ampli? er output. Cin: inverting input. +in: noninverting input. v + : positive supply. vC: negative supply. shdn a : shutdown pin of ampli? er a, active low and only available with the ltc 6087dd. an internal current source pulls the pin to v + when ? oating. shdn b : shutdown pin of ampli? er b, active low and only available with the ltc 6087dd. an internal current source pulls the pin to v + when ? oating. nc: not internally connected exposed pad: connected to v C . rail-to-rail input the input stage of ltc6087/LTC6088 combines both pmos and nmos differential pairs, extending its input common mode voltage to both positive and negative supply voltages. at high input common mode range, the nmos pair is on. at low common mode range, the pmos pair is on. the transition happens when the common voltage is between 1.3v and 0.9v below the positive supply. achieving low input bias current the dd and dhc packages are leadless and make contact to the pcb beneath the package. solder ? ux used during the attachment of the part to the pcb can create leakage current paths and can degrade the input bias current per- formance of the part. all inputs are susceptible because the backside paddle is connected to v C internally. as the input voltage or v C changes, a leakage path can be formed and alter the observed input bias current. for lowest bias current use the ltc6087/LTC6088 in the leaded msop/gn package. with ? ne pcb design rules, you can also provide a guard ring around the inputs. for example, in high source impedance applications such as ph probes, photo diodes, strain gauges, et cetera, the low input bias current of these parts requires a clean board layout to minimize additional leakage current into a high impedance signal node. a mere 100g of pc board resistance between a 5v supply trace and input trace near ground potential adds 50pa of leakage current. this leak- age is far greater than the bias current of the operational ampli? er. a guard ring around the high impedance input traces driven by a low impedance source equal to the input voltage prevents such leakage problems. the guard ring should extend as far as necessary to shield the high impedance signal from any and all leakage paths. figure 1 shows the use of a guard ring in a unity-gain con? guration. in this case the guard ring is connected to the output and is shielding the high impedance noninverting input from v C . figure 2 shows the inverting gain con? guration. figure 1. sample layout. unity-gain con? guration. using guard ring to shield high impedance input from board leakage figure 2. sample layout. inverting gain con? guration. using guard ring to shield high impedance input from board leakage applications information ltc6087 r out in C in + v C leakage current no leakage current guard ring no solder mask over the guard ring 60878 f01 ltc6087 60878 f02 r r out in C in + v C v in gnd
ltc6087/LTC6088 10 60878fa applications information rail-to-rail output the output stage of the ltc6087/LTC6088 swings within 30mv of the supply rails when driving high impedance loads, in other words when no dc load current is present. see the typical performance characteristics for curves of output swing versus load current. the class ab design of the output stage enables the op amp to supply load cur- rents which are much greater than the quiescent supply current. for example, the room temperature short circuit current is typically 45ma. capacitive load ltc6087/LTC6088 can drive capacitive load up to 100pf in unity gain. the capacitive load driving capability increases as the ampli? er is used in higher gain con? gurations. a small series resistance between the output and the load further increases the amount of capacitance the ampli? er can drive. shdn pins pins 5 and 6 are used for power shutdown when the ltc6087 is in the dd package. if they are ? oating, internal current sources pull pins 5 and 6 to v + and the ampli? ers operate normally. in shutdown the ampli? er output is high impedance and each ampli? er draws less than 5a current. this feature allows the part to be used in muxed output applications as shown in figure 3. esd the ltc6087/LTC6088 has reverse-biased esd protection diodes on all inputs and outputs as shown in the simpli? ed schematic. if these pins are forced beyond either supply, unlimited current will ? ow through these diodes. if the current is transient and limited to one hundred milliamps or less, no damage to the device will occur. the ampli? er input bias current is the leakage current of these esd diodes. this leakage is a function of the tem- perature and common mode voltage of the ampli? er, as shown in the typical performance characteristics. noise in the frequency region above 1khz, the ltc6087/LTC6088 shows good noise voltage performance. in this region, noise can be dominated by the total source resistance of the particular application. speci? cally, these ampli? ers exhibit the noise of a 10k resistor, meaning it is desirable to keep the source and feedback resistance at or below this value, i.e., r s + r g ||r fb 10k. above this total source impedance, the noise voltage is dominated by the resistor. at low frequency, noise current can be estimated from the expression in = 2qi b , where q = 1.6 ? 10 C19 coulombs. equating 4ktrf and r 2qi b f shows that for source resistor below 50g the ampli? er noise is dominated by the source resistance. noise current rises with frequency. see the curve noise current vs frequency in the typical performance characteristics section. figure 3. inverting ampli? er with muxed output C + 10k 10k 10k 10k 10pf 10pf out ltc6087 (dd package) sel = 5v, out = Cina sel = 0v, out = C1nb 10k 10k shdn a shdn b fairchild nc7sz04 or equivalent 5v a 5v ina 5v 10k 10k 5v 60878 f03 inb sel C + b
ltc6087/LTC6088 11 60878fa simplified schematic r1 r2 r3 v + v C r4 C + d8 d7 out m8 m9 c1 c2 60878 ss v + v C d5 d6 C + output control m4 m6 a1 a2 m7 m5 i 1 v bias m1 m2 m3 Cin v + v C v + v C d3 d4 +in v C m11 m10 1 a v + v C d1 d2 shdn bias generation note: shdn is only available in the dfn10 package i 2
ltc6087/LTC6088 12 60878fa package description ms8 package 8-lead plastic msop (reference ltc dwg # 05-08-1660 rev f) msop (ms8) 0307 rev f 0.53 0.152 (.021 .006) seating plane note: 1. dimensions in millimeter/(inch) 2. drawing not to scale 3. dimension does not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.152mm (.006") per side 4. dimension does not include interlead flash or protrusions. interlead flash or protrusions shall not exceed 0.152mm (.006") per side 5. lead coplanarity (bottom of leads after forming) shall be 0.102mm (.004") max 0.18 (.007) 0.254 (.010) 1.10 (.043) max 0.22 ?0.38 (.009 ?.015) typ 0.1016 0.0508 (.004 .002) 0.86 (.034) ref 0.65 (.0256) bsc 0 ?6 typ detail ? detail ? gauge plane 12 3 4 4.90 0.152 (.193 .006) 8 7 6 5 3.00 0.102 (.118 .004) (note 3) 3.00 0.102 (.118 .004) (note 4) 0.52 (.0205) ref 5.23 (.206) min 3.20 ?3.45 (.126 ?.136) 0.889 0.127 (.035 .005) recommended solder pad layout 0.42 0.038 (.0165 .0015) typ 0.65 (.0256) bsc
ltc6087/LTC6088 13 60878fa package description dd package 10-lead plastic dfn (3mm 3mm) (reference ltc dwg # 05-08-1699) 3.00 0.10 (4 sides) note: 1. drawing to be made a jedec package outline m0-229 variation of (weed-2). check the ltc website data sheet for current status of variation assignment 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package 0.38 0.10 bottom view?xposed pad 1.65 0.10 (2 sides) 0.75 0.05 r = 0.115 typ 2.38 0.10 (2 sides) 1 5 10 6 pin 1 top mark (see note 6) 0.200 ref 0.00 ?0.05 (dd) dfn 1103 0.25 0.05 2.38 0.05 (2 sides) recommended solder pad pitch and dimensions 1.65 0.05 (2 sides) 2.15 0.05 0.50 bsc 0.675 0.05 3.50 0.05 package outline 0.25 0.05 0.50 bsc
ltc6087/LTC6088 14 60878fa package description gn package 16-lead plastic ssop (narrow .150 inch) (reference ltc dwg # 05-08-1641) gn16 (ssop) 0204 12 3 4 5 6 7 8 .229 ?.244 (5.817 ?6.198) .150 ?.157** (3.810 ?3.988) 16 15 14 13 .189 ?.196* (4.801 ?4.978) 12 11 10 9 .016 ?.050 (0.406 ?1.270) .015 .004 (0.38 0.10) 45 0 ?8 typ .007 ?.0098 (0.178 ?0.249) .0532 ?.0688 (1.35 ?1.75) .008 ?.012 (0.203 ?0.305) typ .004 ?.0098 (0.102 ?0.249) .0250 (0.635) bsc .009 (0.229) ref .254 min recommended solder pad layout .150 ?.165 .0250 bsc .0165 .0015 .045 .005 *dimension does not include mold flash. mold flash shall not exceed 0.006" (0.152mm) per side **dimension does not include interlead flash. interlead flash shall not exceed 0.010" (0.254mm) per side inches (millimeters) note: 1. controlling dimension: inches 2. dimensions are in 3. drawing not to scale
ltc6087/LTC6088 15 60878fa information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. package description dhc package 16-lead plastic dfn (5mm 3mm) (reference ltc dwg # 05-08-1706) 3.00 0.10 (2 sides) 5.00 0.10 (2 sides) note: 1. drawing proposed to be made variation of version (wjed-1) in jedec package outline mo-229 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package 0.40 0.10 bottom view?xposed pad 1.65 0.10 (2 sides) 0.75 0.05 r = 0.115 typ r = 0.20 typ 4.40 0.10 (2 sides) 1 8 16 9 pin 1 top mark (see note 6) 0.200 ref 0.00 ?0.05 (dhc16) dfn 1103 0.25 0.05 pin 1 notch 0.50 bsc 4.40 0.05 (2 sides) recommended solder pad pitch and dimensions 1.65 0.05 (2 sides) 2.20 0.05 0.50 bsc 0.65 0.05 3.50 0.05 package outline 0.25 0.05
ltc6087/LTC6088 16 60878fa linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax: (408) 434-0507 www.linear.com ? linear technology corporation 2007 lt 1207 rev a ? printed in usa part number description comments ltc2051/ltc2052 dual/quad zero-drift op amps 3v v os(max) , 30nv/c v os drift (max) ltc6078/ltc6079 dual/quad micropower precision rail-to-rail op amps 25v v os(max) , 0.7v/c v os drift (max), 1pa i bias(max) ltc6240 single low noise rail-to-rail output op amp 7nv/ hz noise, 1pa i bias(max) , 10v/s slew rate ltc6241/ltc6242 dual/quad low noise rail-to-rail output op amps 7nv/ hz noise, 0.2pa i bias , 18mhz gain bandwidth ltc6244 dual 50mhz rail-to-rail op amps 100 v v os(max) , 1pa i bias , 40v/s slew rate typical applications negative-going and positive-going photodiode tias on 5v supplies almost rail-to-rail (0.3v to v cc ) gain-of-30 current sense ampli? er C + 1/2 ltc6087 5v 5v 1.5k C5v i pd v out 0v C i pd ? r f r f 100k r f 100k 1n4148 c f 2pf c f 2pf photodiode ~3pf photodiode ~3pf C + 1/2 ltc6087 C5v 5v 1.5k C5v 60878 ta02 i pd v out 0v + i pd ? r f 1n4148 note: different devices. not the same ltc6087 C + 1/2 ltc6087 C + 1/2 ltc6087 gain of 15 stage gain of 2 stage 140k 1% 10k 1% out 200 1% 60878 ta03 full-scale v sense = 100mv (3v out). for small signals, input operation is rail-to-rail (v s = 5mv to v cc ). for full scale, input operation is 0.3v to rail. worst-case input offset voltage = 1.8mv. 2n7002 c comp 1nf r comp 10k v cc v s + C load v sense i sense r sense 100 1% related parts

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